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L9830
MONOLITHIC LAMP DIMMER
HIGH EFFICIENCY DUE TO PWM CONTROL AND POWER DMOS DRIVER LOAD CONNECTED TO GROUND CURRENT LIMITATION OVER AND UNDERVOLTAGE PROTECTION ON CHIP THERMAL PROTECTION LIMITED AND PROGRAMMABLE OUTPUT VOLTAGE SLEW RATE OPEN GROUND PROTECTION VERY LOW STANDBY POWER CONSUMPTION LOAD DUMP PROTECTION MINIMIZED ELECTROMAGNETIC INTERFERENCE WIDE CHOICE IN PWM FREQUENCY RANGE LOAD POWER LIMITATION BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
Heptawatt ORDERING NUMBER: L9830
DESCRIPTION The L9830 high side driver is a monolithic integrated circuit realized with Multipower BCD mixed technology to drive resistive or inductive loads in PWM mode with one side connected to ground.
November 1992
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L9830
PIN CONNECTION (Top view)
PIN FUNCTION
PIN 1 2 3 4 5 6 7 NAME VS BS OSC GND PRO IN OUT DESCRIPTION Common supply connection also Drain of the power DMOS. A capacitor connected between this pin and the Source of the power DMOS pin Out gives the possibility to bootstrap the gate driving voltage of the power DMOS. A capacitance CT connected between GND and this terminal determines the PWM switching frequency. Common ground connection. A resistor connected between this pin and GND provide the possibility to programming the output voltage slew rate, the PWM oscillator frequency and the short current value. Analog input for controlling the PWM ratio, related to V S. Source connection of the internal power DMOS.
ABSOLUTE MAXIMUM RATINGS
Symbol VS VDS ViN IS IOR Ptot Tamb Tj Tstg Supply Voltage Drain Source Voltage Input Voltage Supply Current Output Reverse Current Power Dissipation at Tcase 75C Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Parameter Value 60 60 -0.3V up to VS +0.3V 0.2 -2 37.5 -40 to +85 -40 to 150 -65 to 150 A A W C C C Unit V V
THERMAL DATA
Symbol Rth j-case Thermal Resistance Junction-case Description Max Value 2 Unit C/W
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L9830
ELECTRICAL CHARACTERISTICS (6V VS 16V; -40C Tamb 85C, unless otherwise specified)
Symbol Iqo Parameter Operating Quiescent Current VS - 0.7V Iqo = 11.3 + 0.67mA RP Iqs VINSB VINSBhys VINH IIN VSL VSLhys VSLPL VSH VSHhys VSLD ICLD TST TSThys KTi KTe Standby Current Input Standby High Threshold VIN/VS Input Standby Hysteresis Input High Threshold Input Current Low Supply Voltage Disable High Threshold Low Supply Voltage Disable Hysteresis Load Power Limitation Start Supply Voltage High Supply Voltage Disable High Threshold High Supply Voltage Disable Hysteresis Load Dump Supply Voltage Threshold Load Dump Clamping Current Thermal Shutdown Temperature Thermal Shutdown Temperature Hysteresis Internal PWM Frequency Constant (without RP) External PWM Frequency Constant fo = KT/CT fo = 1 KTe C TRP Iq = 50mA VS = 60V VIN VINH, fon ton = 0.96 fo x ton = 1 VS VSLPL -0.3 VIN VS+0.3V 5 -300 12 16 -350 45 100 150 -50 1000 0.220 Test Condition VIN = VS RP R P = 30K VIN = 0 j 100C 0 0.1 -350 0.95VS 1 5.5 -100 13.0 17.8 -190 52 150 175 -40 2000 0.250 2.4 8.5 200 0.15 -190 6 18 600 0.2 -50 VS+0.3V 5 6 -50 17 20 -50 55 300 200 -30 3000 0.350 A V mV V V mV V mA C C Hznf mV mA mA A Min. Typ. Max. Unit
30K R P 500K Iosi Iose Internal Short Current Limitation (without R P) (4) External Programmable Short Current Limit (30K RP 500K) (3) Static Drain Source on Resistance Internal Fixed Output Voltage Slew Rate (without R P) (1) External Programmable Output Voltage Slew Rate (30K RP 500K) (2) VS = 12V VS = 12V, RP = 125K VS 9V, IO = 1A VS = 12V; 5 RL 7 Tamb = 25C VS = 12V, RP = 125K R L = 6 Tamb = 25C 50 50 50 50 3 5 6 6 9 10 A A
RDS Si Se
190 120 120 120 120
380 230 250 200 250
m V/ms V/ms V/ms V/ms
Notes: (1) Si = VS 11.16 (2) Se = 1 - 7.26 Vms ms
(3) IOSP = ( VS - 0.6V )
64260 RP
(4) IOS = ( VS - 0.6V ) 0.514
RL
RP
VS - 0.65V V 6 1.47 10 RL + 0.32 msA
A V
If R P is not present in application an internal equivalent resistor can be inserted in the calculation with a typical value of RP = 125K
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L9830
FUNCTIONAL DESCRIPTION To control the power of the load with a POWERMOS transistor in the switched mode, its gate must be driven with a PWM signal. The amplitude of the gate driving pulse must guarantee that the Power DMOS transistor will be completely saturated during the ON phase. To generate the necessary gate driving voltage a charge pump circuit is required. With this circuit a gate voltage of 2 (VS - 1.5V) VS + 16V typically will be obtained. The slope of the leading and trailing edge of the gate driving pulse is defined with an internal capacitor. The important criteria for the dimensioning of the output voltage slope are the electromagnetic radiation and the power dissipation of the Power DMOS. The typical value of the output pulse slope is in the range of 120V/ms to fullfill automotive radiation requirements. The output pulse slope is directly related to the value of the supply voltage VS and in a wide range programmable through the programming resistance RP.
S= dVout dIload RL VS - 0.65V 10 V = = RL 1.47 dt dt RP RL + 0.32 Ams
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pacitors and should be in the range of CBS 100nF The switching frequency "fO" is defined with a triangle oscillator and it's programmed with the capacitor CT, or CT and RP if a greater precision is required. fO = KT/CT (without RP) 1 (with RP) 4CTRP The modulation factor of the PWM driving signal of the external Power DMOS transistor is defined with the voltage level at the analog input. Fig. 1 shows the typical transfer curve giving the PWM factor as a function of the input/supply voltage ratio. For higher supply voltage values, the power limitation circuitry will linearly reduce the PWM ratio to achive a constant load power to extend the lamps life time. The input voltage is referred to the supply voltage. The regulation of the PWM factor can be realized with a potentiometer connected to the supply voltage and the analog input, see the typical application circuit diagram. The maximum load current in the short circuit condition is limited internally with a sense DMOS cell. The value of the short current is a multiple of the programming current flowing through RP or the internal fixed resistance. Threfore this short current fO =
The value of the gate voltage slope due to the POWERMOS parasitic capacitors must be in a relation to the charge pump performance. For fast gate voltage variation the bootstrap option can be used. The bootstrap capacitance should have a relation greater than 50 to the DMOS parasitic caFigure 1: Transfer Characteristc
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L9830
value is supply voltage dependent to achieve in any condition the lamp required warm up current which will be normally two or three times higher. VS - 0.6V 64260 IOSe = RP If the short current condition is detected the gate will be driven with a DC voltage which value is regulated to maintain the specified current. With this function the switch ON phase for each load will be speeded up. The circuit features also a protection which allows to withstand high overvoltage for a limited time (load dump in automotive application). Above the VSH threshold the gate driving of the POWERMOS transistor is switched OFF and the gate is held at the GND potential. When the VBAT rises above the internal supply clamp voltage VSLD the clamping diode becomes active with a serial resistance of RLD and the gate voltage is floating with the GND potential. At this time the current flowing through the load is not limited. In this condition the load voltage can be calculated to VL = VS = VSLD - VSGS VGS << VSLD This device is protected against temperature destruction through an internal power dissipation protection. The total power dissipation of the device can be calculated with:
for VSL VS VSLPL: RDS RDS fO RDS 2VS (1- Ptot = VS2 + ) ( 1- ) (1 + ) 2 S RDS + RL RDS +RL RDS + RL (RDS + RL) and for VSLPL VS VSH: Ptot = V2 SLPL VS2 fO RON 2 RDS + (1- ) ( RDS + RL ) S RON + RL
Figure 2: Total Power Dissipation Characteristic
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L9830
Figure 3: Application Circuit Diagram for Dashboard Dimming
VS < VSLD
Note: All node voltage are referred to ground pin GND. The currents flowing in the arrow direction are assumed positive.
Figure 4: Application Circuit Diagram for Dashboard Dimming with Optimized Device Power Dissipation
Note: All node voltage are referred to ground pin GND. The currents flowing in the arrow direction are assumed positive.
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L9830
HEPTAWATT PACKAGE MECHANICAL DATA
DIM. A C D D1 E F F1 G G1 G2 H2 H3 L L1 L2 L3 L5 L6 L7 M M1 Dia 3.65 2.6 15.1 6 2.8 5.08 3.85 0.144 10.05 16.97 14.92 21.54 22.62 3 15.8 6.6 0.102 0.594 0.236 0.110 0.200 0.152 2.41 4.91 7.49 2.54 5.08 7.62 2.4 1.2 0.35 0.6 mm MIN. TYP. MAX. 4.8 1.37 2.8 1.35 0.55 0.8 0.9 2.67 5.21 7.8 10.4 10.4 0.396 0.668 0.587 0.848 0.891 0.118 0.622 0.260 0.095 0.193 0.295 0.100 0.200 0.300 0.094 0.047 0.014 0.024 MIN. inch TYP. MAX. 0.189 0.054 0.110 0.053 0.022 0.031 0.035 0.105 0.205 0.307 0.409 0.409
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L9830
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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